This project is one of several SCALE SURF research projects. SCALE projects are restricted to students who are U.S. Citizens. By applying to this project, you can be considered for any of the SCALE projects with one application. See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.

In 2017, a large-scale, 3D integrated quantum processor was demonstrated by MIT Lincoln Laboratory using heterogeneous 3D integration to create an architecture that enables the use of the third dimension without sacrificing qubit performance [D. Rosenberg, et al., Nature 2017]. In these quantum applications, conventional Sn-based solder bumps are not reliable while Indium and bismuth-based solders are promising for 3D integration at low temperatures. In this topic, new cryogenic compatible packaging materials and cryogenic superconducting multi-chip bonding techniques are needed to further explore and investigate the microelectronics devices and packages at low/cryogenic temperatures.

Reference: Rosenberg, D., et al. "3D integrated superconducting qubits." npj quantum information 3.1 (2017): 1-5.)

In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.

For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.

Advanced Packaging, Heterogeneous Integration, Material Processing and Characterization, Microelectronics, Nanotechnology, System-on-a-Chip

• Electrical Engineering
• Materials Engineering
• Mechanical Engineering

1. Microelectronics, micro/nanotechnology courses 2. Clean room fabrication experience 3. Enthusiasm for material fabrication and characterizations 4. Familiar with SEM, TEM analysis

ME

Tiwei Wei

This project is one of several SCALE SURF research projects. SCALE projects are restricted to students who are U.S. Citizens. By applying to this project, you can be considered for any of the SCALE projects with one application. See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.

Interposer is one of the most potential solutions for future 3D integration with ultrafine pitch. Silicon interposer has been developed in both industry and academia. However, silicon interposer has limitations, such as low productivity due to limited wafer size, extra expensive semiconductor fabrication processes, and poor electrical properties like insert loss and signal crosstalk. On the contrary, glass can be one kind of promising material as an interposer because of its excellent properties, such as good electrical resistivity, relatively low CTE compared to organic material, and possible high productivity with big panel sizes provided by glass suppliers.

Recent research studies have mainly focused on three challenges in glass interposer technology: (1) formation of the fine pitch via, which is more difficult than through silicon via (TSV) due to the unfavorable etching process ; (2) via metallization and via filling process, which become much more complicated because of the rough morphology of TGV surface, and difficulty to fill the tapered via through Damascus electroplating; (3) reliability concern, which is caused by brittleness and poor mechanical strength of glass.

Through glass via fabrications
Reference: Wei, T. W., Cai J.*, et al. Performance and reliability study of TGV interposer in 3D integration[C]//2014 IEEE 16th Electronics Packaging Technology Conference (EPTC). IEEE, 2014: pp. 601-605.

In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.

For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.

Advanced Packaging, Heterogeneous Integration, Material Modeling and Simulation, Material Processing and Characterization, Microelectronics, Nanotechnology, System-on-a-Chip

• Electrical Engineering
• Mechanical Engineering
• Materials Engineering

1. Microelectronics, micro/nanotechnology courses 2. Clean room fabrication experience 3. Enthusiasm for material fabrication and characterizations 4. Familiar with SEM, and TEM analysis.

ME

Tiwei Wei

This project is one of several SCALE SURF research projects, and is restricted to US citizens. If you are interested in more than one SCALE SURF project, you can apply to all of them with one application. ** Be sure to address each project by name in your application. ** See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.

Low-melting point metals based on tin are used to connect semiconductor packages to circuit boards. The specific solder composition that is chosen for a product depends on the product's use conditions, for example, consider the differences in use conditions for a cell phone, an implanted pace maker, strapped onto a car engine, and in a satellite.. This project explores the performance and manufacturing differences between solders for different use cases as a function of composition and application. We are collaborating with researchers from Auburn University, the University of Maryland, Raytheon, BAE Systems, the Department of Defense to develop a guide for solder selection for aerospace and defense applications. These researchers have backgrounds in materials engineering, mechanical engineering, industrial engineering, and electrical engineering, so many different skill sets are needed and you will see different perspectives. This project will require extensive review of the literature and performing materials characterization, processing, manufacturing, and reliability experiments. Student researchers will learn a wide range of materials and mechanical property, processing, and characterization techniques and will work closely with faculty and graduate students from Materials Engineering and Mechanical Engineering.

To apply to a SCALE SURF project, go to the SURF website: https://engineering.purdue.edu/Engr/Research/EURO/SURF/Research/Y2023
In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.

For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.

Preferred majors:
• Materials Engineering
• Mechanical Engineering

Required Experience and Skills:

Desired experience:
• Experience with programming in Python, C/C++, and/or MATLAB.
• Enthusiasm for scientific research.
• Understanding of introductory materials science and engineering concepts.

Academic Years Eligible:
Rising juniors and seniors with the desired experience will be preferred, but rising sophomores are also eligible to apply.

Advanced Packaging, Heterogeneous Integration, Material Processing and Characterization, Microelectronics

• Materials Engineering

• Experience with programming in Python, C/C++, and/or MATLAB. • Enthusiasm for scientific research. • Understanding of introductory materials science and engineering concepts.

Materials Engineering

Carol Handwerker

This project is one of several SCALE SURF research projects, and is restricted to US citizens. If you are interested in more than one SCALE SURF project, you can apply to all of them with one application. ** Be sure to address each project by name in your application. ** See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.

Heterogeneous integration of different dielets (processor, memory, RF, etc.) has made rapid strides in the last decade driven by the development of three-dimensional (3D) integration, fan-out wafer-level packaging, and interposers. A key requirement of package scaling is the reduction of the I/O pitch, which requires elimination of solder and micro-solder bumps. Scaling of solder bumps below 40 µm pitch is challenging due to multiple issues, such as solder extrusion, bridging and intermetallic compound (IMC) formation. Therefore, micro and nano-Cu interconnects using Cu to Cu thermal compression bonding and hybrid bonding have been demonstrated for next generation heterogeneous integration. However, nano-Cu interconnects suffer from electromigration related failures at sub-micron pitch sizes. Here we propose Cu, Ag or cobalt composite with graphene or reduced graphene oxide for compliant and high conductivity interconnects. Graphene is a 2D array of sp2-bonded carbon atoms and is known to have extraordinary electrical and mechanical properties. The carrier mobility of graphene is 2.5 x 104 cm2V-1s-1 and the maximum current carrying capacity is up to 108 Acm-2, therefore, graphene-based materials show great potential for future interconnect technologies such as Cu-graphene or Co-graphene or Ag-graphene composites. SURF student will prepare Cu-graphene, Co-graphene, Ag-graphene composites and measure thermal conductivity using a TLM test structure. Multi-photon 3D printing will also be explored to define nanometer feature size. Future work will include effect of these composites on mechanical, thermal and electromigration properties.

In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.

For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.

Advanced Packaging, Heterogeneous Integration, Material Processing and Characterization, Microelectronics, Nanotechnology

• Mechanical Engineering,
• Materials Engineering
• Chemical Engineering

MSE230 or introductory materials course. Training will be provided on SEM and other tools needed.

School of Mechanical Engineering

Shubhra Bansal

This project is one of several SCALE SURF research projects, and is restricted to US citizens. If you are interested in more than one SCALE SURF project, you can apply to all of them with one application. ** Be sure to address each project by name in your application. ** See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.

Low-melting point metals based on tin are used to connect semiconductor packages to circuit boards. The specific solder composition that is chosen for a product depends on the product's use conditions, for example, consider the differences in use conditions for a cell phone, an implanted pace maker, strapped onto a car engine, and in a satellite. While most solder alloys have melting points between 217 °C (high temperature Pb-free alloys) and 183 °C (Sn-Pb eutectic), a new generation of Sn-Bi solder alloys are being developed that have melting points around 139 °C to lower soldering processes in order to minimize warpage-induced asse mbly defects. This project explores the alloy design space for Sn-Bi alloys in terms of performance and manufacturing as a function of composition and application. We are collaborating in this research with a range of microelectronics companies, including Intel, Texas Instruments, Nvidia, AMD, and Macdermid Alpha. Student researchers will learn a wide range of materials and mechanical property, processing, and characterization techniques and will work closely with faculty and graduate students from Materials Engineering and Mechanical Engineering.

To apply to a SCALE SURF project, go to the SURF website: https://engineering.purdue.edu/Engr/Research/EURO/SURF/Research/Y2023
In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.

For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.

Advanced Packaging, Heterogeneous Integration, Material Processing and Characterization

• Materials Engineering
• Mechanical Engineering

Materials Engineering

Carol Handwerker

This project is one of several SCALE SURF research projects, and is restricted to US citizens. If you are interested in more than one SCALE SURF project, you can apply to all of them with one application. ** Be sure to address each project by name in your application. ** See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.

Semiconductor Research Corporation (SRC) identifies the need for solders with peak reflow temperature less than 140 ℃ for Si heterogeneous integration and high temperature solders for SiC heterogeneous integration. Sn-based solders have shown promise for low-temperature regime and Bi-based solders are promising for high temperature applications. Both these classes of solder materials have their own challenges. For fine pitch interconnects, conventional Sn-based solder materials suffer from drawbacks including die stress due to high reflow temperatures, intermetallic formation, Sn-whisker growth and electromigration. Bi-based solders suffer from wettability issues. Here we to propose to develop a disruptive approach to tailoring properties of solder materials by changing their structural dimensionality. For example, Melting point depression of 26.6 ℃ has been observed for SAC nanoparticles with an average diameter of 18 nm for extremely fine pitch 2-8 µm applications. However, the difficulty lies in the reflow process due to formation of oxide and thereby impeding the coalescence of molten core particles. Reducing fluxes and acidic treatments have proven to be promising for oxide removal, however, the acidity of solution can alter the particle size, morphology and package integrity. Our intent is to explore the effect of the number of atomic layers on solder properties, which can be translated into a commercial process, if successful. Precursor based solution processing can be used to process quantum dots, 1D, 2D structures of these solders that should conceptually result in suppression of melting temperature and reduction in Sn-whisker growth. In the proposed project we will study the effect of dimensionality on Sn-Ag-Cu, Sn-Bi, Sn-In low temperature and Bi-based high temperature solders. SURF student will develop proof-of-concept with commercially available Sn-Ag-Cu and Sn-Bi solder and use ion-milling to exfoliate monolayers of the material. The monolayers will be passivated with organic ligands and subsequently melting temperature will be measured using differential scanning calorimetry (DSC). We will collaborate with GE Global Research and University of Binghamton for development of Bi-based high temperature solders. Future work will include development of processing methods for dimensionally modified solders, integration, reliability studies, etc.

In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.

For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.

Advanced Packaging, Heterogeneous Integration, Material Processing and Characterization, Microelectronics

• Mechanical Engineering

Mechanical Engineering

Shubhra Bansal

This project is one of several SCALE SURF research projects. SCALE projects are restricted to students who are U.S. Citizens. By applying to this project, you can be considered for any of the SCALE projects with one application. See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.

For the typical 3D integration scheme, die-to-wafer bonding is a key technology that can enable the stacking of different chips, such as logic, memory, or power devices. Compared with wafer-to-wafer bonding, it is challenging for die-to-wafer bonding to achieve high throughput while maintaining a high alignment accuracy. Researchers have been investigating different self-alignment technologies to improve the high-precision chip alignment accuracy for die-to-wafer bonding, such as Surface tension-driven with hydrophilic chip surfaces. In this topic, we will explore innovative self-alignment methods for advanced die-to-wafer bonding, enabling high throughput heterogeneous integration.

Reference: Fukushima, Takafumi, et al. "Self-assembly technologies with high-precision chip alignment and fine-pitch microbump bonding for advanced die-to-wafer 3D integration." 2011 IEEE 61st Electronic Components and Technology Conference (ECTC). IEEE, 2011.)

In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.

For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.

Advanced Packaging, Composite Materials and Alloys, Fluid Modelling and Simulation, Heterogeneous Integration, Material Modeling and Simulation, Material Processing and Characterization, Microelectronics, Nanotechnology, Thermal Technology

• Electrical Engineering
• Mechanical Engineering
• Materials Engineering

1. Microelectronics, micro/nanotechnology courses 2. Clean room fabrication experience 3. Enthusiasm for material fabrication and characterizations 4. Familiar with SEM, TEM analysis 5. Fluid mechanics Academic Years Eligible: Rising juniors and seniors with the desired experience will be preferred, but rising sophomores are also eligible to apply.

ME

Tiwei Wei